1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which is effective in suppressing the optical proximity effects.
2. Description of the Related Art
The following terms used in the present specification shall have the following meanings.
“Active transistor” refers to a transistor which contributes to a desired function of a circuit using its operational characteristics. “Inactive transistor” refers to a transistor which does not contribute to a desired function of a circuit. Non-uniformity in gate shape of inactive transistors does not affect the desired function of the circuit. “Transistor” can refer to any of an active transistor and an inactive transistor.
Typical examples of the inactive transistor include: a P-channel transistor whose gate potential is fixed to the supply potential, or N-channel transistor whose gate potential is fixed to the ground potential, and which is maintained in an OFF state (hereinafter, referred to as “off-transistor”); a P-channel transistor whose gate potential is fixed to the ground potential and whose source and drain potentials are fixed to the supply potential, or N-channel transistor whose gate potential is fixed to the supply potential and whose source and drain potentials are fixed to the ground potential, and which is employed as a capacitor between the power supply and the ground (hereinafter, referred to as “capacitance transistor”); a transistor whose source and drain potentials are fixed to an equal potential such that no current flows; and a transistor which serves to maintain the drain potential equal to the supply potential or ground potential (hereinafter, referred to as “potential-fixing transistor”).
“Gate” refers to part of a transistor formed of polysilicon, or the like, which is functionally combined with a diffusion region to constitute the transistor or refers to a “dummy gate” which is not a constituent of a transistor.
Hereinafter, a transistor, a typical standard cell formed using the transistor, and a semiconductor integrated circuit formed using the standard cell are described in this order with reference to the drawings.
FIG. 15A shows a P-type transistor Tp which is formed by P-type diffusion regions Dp, a gate G, and an N-type well NW. FIG. 15B shows an N-type transistor Tn which is formed by N-type diffusion regions Dn, a gate G, and a P-type well PW. The gate G of the transistors, which is made of materials including polysilicon and other components, is sandwiched by the diffusion regions Dp (or Dn). The source and drain of the transistors are formed by the diffusion regions Dp (or Dn). Throughout the drawings, the gate width of the gate G is denoted by “W”, and the gate length of the gate G is denoted by “L”. With varying gate widths W and gate lengths L, a variety of transistor characteristics are acquired as desired.
FIG. 16 shows a standard cell formed using the transistors of FIG. 15A and FIG. 15B. Referring to FIG. 16, the standard cell C includes: a diffusion region Dbn for supplying a substrate potential to P-type transistors Tp1 and Tp2, N-type transistors Tn1 and Tn2, and P-type transistors Tp1 and Tp2; a diffusion region Dbp for supplying the substrate potential to the N-type transistors Tn1 and Tn2; a metal line Mvdd for supplying a supply potential to the sources of the P-type transistors Tp1 and Tp2; a metal line Mvss for supplying a ground potential to the sources of the N-type transistors Tn1 and Tn2; and an N-type well NW and a P-type well PW. The distance between the gates of the transistors is denoted by “S”. It should be noted that the diffusion regions of the transistors, the gate G, gate width W and gate length L are not indicated in FIG. 16 in order to avoid repeating the descriptions of FIG. 15. The standard cell C shown in FIG. 16 is a typical standard cell example and, however, various other standard cells are possible with flexible arrangements and wirings of transistors having various shapes.
FIG. 17 shows a semiconductor integrated circuit including a plurality of standard cells. As shown in FIG. 17, the standard cells (C1, C2, C3, . . . ) are adjacently aligned in a direction perpendicular to the direction in which the gates of their transistors are extended, thereby forming a standard cell row. (Hereinafter, the direction in which the gates are extended is referred to as “vertical direction” for convenience of description, and the direction perpendicular to the vertical direction is referred to as “transverse direction”.) A plurality of such standard cell rows are located side by side in the vertical direction, which are interconnected to one another to realize an LSI having a desired function. In this process, the standard cells are located such that the N-type wells NW, P-type wells PW, diffusion regions Dbn, diffusion regions Dbp, metal lines Mvdd and metal lines Mvss (none of which are shown) of the respective standard cells are common among or adjoining between the standard cells and therefore have shapes extended in the transverse direction without discontinuity.
Hereinafter, disadvantages resulting from non-uniformity in the gate dimensions of the transistors in this semiconductor integrated circuit are described.
The primary factors in variation of propagation delay time in the semiconductor integrated circuits include the operation supply voltage, temperature, and process variations. The semiconductor integrated circuits need to be designed such that the operation of the circuits can be secured even when all the factors in the variation are in the worst conditions. Especially, the gate length of a transistor is an important factor in definition of the operation of the transistor, and the influence of non-uniformity in the gate lengths constitutes considerably large part of the process variations. In recent years, as the miniaturization of transistors has been advanced, the gate length has been further decreasing so that the gate length non-uniformity constitutes a larger proportion in general. Therefore, the design margins need to be increased as the variation of the propagation delay time increase. Thus, it is difficult to provide a high-performance semiconductor integrated circuit.
In a typical manufacture process of semiconductor integrated circuits, the photolithography step including resist application, exposure and development, the etching step for patterning of elements with resist masks, and the resist removal step are repeated to form an integrated circuit on a semiconductor substrate. The formation process of the gates of transistors also includes the photolithography step, the etching step, and the resist removal step. In exposure at the photolithography step, pattern dimensions equal to or smaller than the exposure wavelength result in large errors between the layout dimensions defined at the time of designing and the pattern dimensions on a manufactured semiconductor substrate due to the optical proximity effects produced by diffracted light.
In manufacture of a semiconductor integrated circuit, in patterning of wirings and other elements via drawing or exposure, corrections for improvement in dimension accuracy of the pattern are indispensable for preventing occurrence of optical proximity effects. One of the techniques of correcting the optical proximity effects is OPC (Optical Proximity effect Correction). According to the OPC, a gate length non-uniformity resulting from the optical proximity effects is estimated from the distance between a gate and another gate pattern adjacent to the gate, and the mask value of a photoresist used for formation of the gate is corrected in advance such that the non-uniformity is compensated for, whereby the gate length value of a gate actually formed after exposure is maintained constant.
On the other hand, the OPC performed on the gate mask can disadvantageously increase the delay of TAT (Turn Around Time) and the amount of process efforts. Especially because the gate pattern has not conventionally been standardized and the gate length and gate interval are thus varying over a whole chip, the corrections based on the OPC technique have been requiring a huge amount of process efforts.
To avoid such a disadvantage, it has been proposed to limit the variety of gate length and gate interval to one or several optional values in the layout process. With this proposed solution, the gate length value of a gate actually formed can be maintained constant by designing circuits using a limited number of gate length values or inserting dummy gates for achieving uniform gate intervals, without gate mask corrections based on OPC. Thus, non-uniformity in the gate lengths due to the optical proximity effects can be suppressed.
FIG. 18 shows a standard cell example which is designed to be used when the gate length and gate interval are respectively limited to one option. In the standard cell of FIG. 18, the transistor gates G1, G2, . . . and G8 have equal gate length L and are located with constant gate intervals S. Namely, to suppress non-uniformity in the gate lengths among the gates G2, G3, G6 and G7 of the active transistors due to the optical proximity effects, the standard cell is furnished with the dummy gates G1, G4, G5 and G8 such that the gate intervals and the gate lengths are uniform.
FIG. 19 shows a conventional semiconductor integrated circuit which is designed using such standard cells as shown in FIG. 18. Referring to FIG. 19, the standard cells (C1, C2, C3, . . . ) are arranged in the transverse direction such that the dummy gates are shared at the borders between the standard cells. Since all the active transistors in the semiconductor integrated circuit have equal gate lengths and same gate intervals, the gate length value of the gates actually formed can be maintained constant, and therefore, the non-uniformity in the gate lengths due to the optical proximity effects can be suppressed.
Known technology documents, prior to the present application, in the art fields the inventions of the present application relate to are as follows:
(Patent Document 1) Japanese Laid-Open Patent Publication No. 10-32253
(Patent Document 2) Specification of U.S. Pat. No. 7,137,092
(Patent Document 3) Japanese Laid-Open Patent Publication No. 2007-12855
As described above, the finer dimensions of the transistors have been accompanied by shortening of the gate lengths, resulting in larger influence of the optical proximity effects due to diffracted light in gate exposure. In addition, the influence of the optical proximity effects disadvantageously varies according to the patterns surrounding the gates.
For example, in the semiconductor integrated circuit shown in FIG. 19, the gate of a centrally-located active transistor is accompanied by two or more neighboring gates located on the both sides. Specifically, the gate Ga, for example, is accompanied by the gates Ga1 and Ga2 on the left side and by the gates Ga3 and Ga4 on the right side. On the other hand, the gate of an active transistor located at an end of a standard cell row can be accompanied only by one neighboring gate. For example, the gate Gb is accompanied only by the dummy gate Gb1 on the left side, with no neighboring gate on the other (right) side.
The influence of the optical proximity effects on a gate which is located at an end of a standard cell row and which is accompanied only by one neighboring gate, such as the gate Gb, is greatly different from that on a gate which is accompanied by two or more neighboring gates on each side, such as the gate Ga. Thus, the magnitude of variations in the gate dimensions is greatly different therebetween.
Thus, uniformly performing the correction processes of OPC over the whole semiconductor integrated circuit allows the existence of a gate in which variations in the gate dimensions are not necessarily appropriately corrected, leading to errors in the circuit operations. A conceivable alternative solution is separately performing different corrections of OPC on a gate which is located at an end of a standard cell row and which is accompanied only by one neighboring gate, but this solution undesirably entails an increase in time for correction.